# This is a maptable for nelsis <--> seadif conversion, generated/maintained by 'nelsea'
# Written on: Tue Dec 22 11:38:11 1992
# You can edit this file to control the mapping process
# Each line contains the name of a nelsis cell and its corresponding seadif cell
# The status field may contain the following values:
#    'written'       the cell was succesfully written into seadif resp. nelsis
#    'primitive'     the cell is a primitive which should not be read or converted
#    [anything else] the cell will be written if necessary
#
#    N E L S I S     |                   S E A D I F                     | nelsis->sdf sdf->nelsis
# view    cellname   | library      function     circuit      layout     |   status      status
#--------------------+---------------------------------------------------+------------------------
 layout   osc10        oplib1_93    osc10        osc10        osc10          
 layout   no310        oplib1_93    no310        no310        no310          
 layout   na310        oplib1_93    na310        na310        na310             
 layout   na210        oplib1_93    na210        na210        na210             
 layout   mu210        oplib1_93    mu210        mu210        mu210             
 layout   mu111        oplib1_93    mu111        mu111        mu111             
 layout   mir_pout     oplib1_93    mir_pout     mir_pout     mir_pout          
 layout   mir_pin      oplib1_93    mir_pin      mir_pin      mir_pin           
 layout   mir_nout     oplib1_93    mir_nout     mir_nout     mir_nout          
 layout   mir_nin      oplib1_93    mir_nin      mir_nin      mir_nin           
 layout   lp3x3        oplib1_93    lp3x3        lp3x3        lp3x3             
 layout   ln3x3        oplib1_93    ln3x3        ln3x3        ln3x3             
 layout   iv110        oplib1_93    iv110        iv110        iv110             
 layout   ex210        oplib1_93    ex210        ex210        ex210             
 layout   dfr11        oplib1_93    dfr11        dfr11        dfr11             
 layout   dfn10        oplib1_93    dfn10        dfn10        dfn10             
 layout   de211        oplib1_93    de211        de211        de211             
 layout   no210        oplib1_93    no210        no210        no210             
 layout   buf20        oplib1_93    buf20        buf20        buf20             
 circuit  Osc10        oplib1_93    osc10        osc10        $dummy            
 circuit  No310        oplib1_93    no310        no310        $dummy            
 circuit  No210        oplib1_93    no210        no210        $dummy            
 circuit  Na310        oplib1_93    na310        na310        $dummy            
 circuit  Na210        oplib1_93    na210        na210        $dummy            
 circuit  Mu210        oplib1_93    mu210        mu210        $dummy            
 circuit  Mu111        oplib1_93    mu111        mu111        $dummy            
 circuit  Iv110        oplib1_93    iv110        iv110        $dummy            
 circuit  Ex210        oplib1_93    ex210        ex210        $dummy            
 circuit  Dfr11        oplib1_93    dfr11        dfr11        $dummy            
 circuit  Dfn10        oplib1_93    dfn10        dfn10        $dummy            
 circuit  De211        oplib1_93    de211        de211        $dummy            
 circuit  Buf20        oplib1_93    buf20        buf20        $dummy            
 circuit  mir_pout     oplib1_93    mir_pout     mir_pout     $dummy            
 circuit  mir_pin      oplib1_93    mir_pin      mir_pin      $dummy            
 circuit  mir_nout     oplib1_93    mir_nout     mir_nout     $dummy            
 circuit  mir_nin      oplib1_93    mir_nin      mir_nin      $dummy            
 circuit  lp3x3        oplib1_93    lp3x3        lp3x3        $dummy            
 circuit  ln3x3        oplib1_93    ln3x3        ln3x3        $dummy            
